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LSI Chip intel Programmable Peripheral Interface (PPI) 8255

Intel Chip PPI 8255


Image courtesy of wikipedia.org

Chip LSI internal configuration PPI 8255 shows the figure 1. In figure 1, pin IC 8255 consists of 3 groups:
1. Read / Write Control Logic
2. Data Bus Buffer
3. Input / Output Ports

Image courtesy of wikipedia.org


READ / WRITE CONTROL LOGIC

Groups Read / Write Control Logic organize all data and controls, both internal transfers Form and Form of Transfer externally. ACCEPT singer group input from address bus and bus control CPU, the group later realize Ke - Control group. Pin - pin Of The Read / Write Control Logic is as follows:

CS (Chip Select)

Low ON signal pin singer will be to enable communication LSI Chip PPI BETWEEN 8255 TO microcomputers.

RD (Read):
Low ON signal pin singer will be to enable the CPU to review read status information OR Data From Chip LSI PPI 8255

WR (Write)
Low ON signal pin singer will be to enable the CPU to write a review OR Data Into PPI control word 8255
A0 and A1:
The input selector is functioning as part of the Joint Control word - the same WITH RD and WR. Basic Operations The Group is controlled by the Read / Write Control Logic singer portrayed ON the table below.

re:
ON logic high reset input will be to clear the contents of the list of controls and harbor ALL To set the input mode.

Control Group A and Group B:

Configuration functions From EVERY port in the software program by. IN AN basically CPU provides output control word addressed to the LSI Chip Control Word 8255. PPI mode provides information about, bit set, bit reset, And Others. Singer configuration is used to initialize the configuration functions review Chip LSI 8255 PPI.

EVERY Control blocks (Group A and Group B) RECEIVE command From the Read / Write Control Logic, And said menerimacontrol Data From internal bus (internal data bus) and execute commands - Commands Right to review arrangements port - port ITU. ON said control registers can only perform write operations, NO can perform read operations.

DATA BUS BUFFER
The data bus is a 3 state buffer 8 bit With operations Operating prayer Arah (both directions), ayng used to review 8255 WITH connect Chip PPI data bus system. Data Sent and received through the data buffer bus, Similarly to review the control word.

PORT INPUT / Output
Port Input / Output Was Part Of The 8255 PPI chip serves as a liaison

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